Combinatorial Aspects of Lower Power Clock Layout Synthesis in VLSI Synchronous Circuits

In a synchronous VLSI design, carrying the heaviest load and switching at high frequency , clock distribution is a major source of power dissipation. Also, circuit speed and chip area have been an important consideration and the delay on the longest path (phase delay) through combinational logic, and the maximum skew among the synchronizing components should be minimized. There have been active research in the area of high-performance and low-power clock routing. This paper gives an overview of a number of combinatorial aspects and highlights the state of the art of currently active research areas on low power clock tree synthesis. Promising future directions and open problems are also investigated.